VHDL Implementation

Implementation of VHDL

Research frequently employs VHDL (VHSIC Hardware Description Language) to design hardware and implement digital systems. Scholars employ VHDL to articulate the operations of digital systems and circuits, subsequently synthesizing and simulating them in preparation for hardware platform implementation.

Hardware acceleration, embedded systems, digital signal processing, and FPGA-based systems are typical research topics in VHDL implementation.

Why VHDL?

• Consequently, the issue arose as these companies were unable to share their code and designs with one another. Additionally, each company submitted their chip design to the Department of Defence (DoD) using a different HDL.

• Consequently, there arose a need for a standardised hardware description language to facilitate documentation, verification, and digital system or circuit design,

VHDL has several advantages, including its vendor-independence, portability, and reusability.

• The software facilitates hierarchical design, allowing for the representation of large and intricate systems as interconnected little components. Furthermore, these components can be further represented as interconnected subcomponents.

• The VHDL programme executes all statements concurrently, unless they are placed within a procedure, function, or process.

• The programme is legible to both humans and machines.

• It adheres to the standards set by IEEE and ANSI.

• It supports various design methodologies such as top-down, bottom-up, and mix.

• It can be used to design combinational, sequential, or mixed digital circuits using three different methods.

1) Data flow

2) Behavioural

3) Organisational

The VHDL Design Flow:

1. The initial step in the VHDL design pipeline is composing the VHDL programme. Numerous manufacturing enterprises, like as XILINX and Altera, offer proprietary software development tools, including XILINX ISE and Altera Quartus, which facilitate the editing, compilation, and simulation of VHDL code. The circuit in this VHDL code is defined using the Resistor Transfer Level (RTL)

2. You can generate Gate-level Netlists using the given VHDL code because it has been compiled. The compiler is able to accomplish its tasks by translating the RTL format of high-level VHDL code into Gate Level.

3. The Netlist is fine-tuned even further to make it more efficient at the Gate Level. The goal of optimisation is to reduce space consumption and increase speed Here is where the design simulation is carried out.

4. ASIC or CPLD/FPGA physical apparatus development or implementation follows the use of the optimised Netlist by place and route software (fitter).The last devices could be tested and verified again using simulation.

The VHDL programme structure comprises a minimum of two components.

• Architecture and Entity

• The design may include supplementary elements like as package declaration, configuration, body, etc., according on the specific requirements.

Declaration of the library:

• The library includes all the standard code segments that are routinely used. This will allow us to consistently employ them. Moreover, this can be distributed over diverse designs.

• The process begins with the keyword “LIBRARY” followed by the name of the library.

• In all VHDL codes, it is customary to utilise three libraries.

• The IEEE library is utilised to define a multilevel logic system.

• The standard library serves as a resource for the VHDL design environment.

• The “work” library is employed to store project work and programme files in the.vhd format.

• The other two libraries are defaults, so you only need to declare the IEEE library in your code.

• The next step is to combine the various parts of the library packages. The name of the library, its packages, and its components are used in conjunction with the USE keyword.

Entity declaration:

To enable communication between the digital circuit and other components and circuits, the entity defines the input-output connections of the circuit.

• It specifies how many inputs were fed into the circuit and how many outputs were extracted from it.

• Any intermediate signals used by the circuit are also declared.

• The keyword ENTITY is required for entity declarations. It is common practice to ask the user to provide an item a name like decoder, mux, adder, counter, etc., while they are creating a circuit. All VHDL programmes are subject to the ubiquitous the programme file name and the entity name must be same requirement.

• The PORT keyword is used to declare the I/O pins of a circuit inside an entity.

• Port_mode, Port_name, and Port_type are used to declare the interface pins, as the name implies.

• The input-output pin can be named by the user using the port_name property. The port_mode property can be one of four types: IN, OUT, INOUT, or BUFFER.

• A read-only input pin is denoted by IN. A write-only output pin is denoted by the symbol OUT. There is just one way to use these pins.

• The INOUT pin is a bidirectional connector that allows for both reading and writing. As an intermediate output, BUFFER is utilised

• After all interfaces are declared, the entity declaration concludes with the keyword END followed by the name of the entity. The port_type can be BIT_VECTOR, BIT, STD_LOGIC, etc.

Architecture

Digital circuit functionality is declared by architecture.

Entity internal features, such as input-output connections, are provided by architecture.

Architects define circuit behaviour as the process by which a circuit converts inputs into the desired output.

ARCHITECTURE is the first keyword in the architecture declaration, which is followed by entity_name and architecture_name.

• The architecture body is initiated using the BEGIN keyword. Statements describing the operation of the circuit are included in the body in a sequential or concurrent fashion.

• The architecture body is concluded with the keywords END followed by the name of the architecture.

• The three main approaches to architectural body modelling are as follows:

• Data flow style, which describes the circuit using concurrent statements

• One approach to circuit modelling is the behavioural style, which relies on sequential assertions to describe the circuit.

• Structural style – this type of modelling describes the circuit by utilising many coupled components.